SH7615 Datasheet, PDF (304/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bits 7 to 0—Wait Control for Areas 3 to 0 (W31 to W00)
• When the CSn space is set as ordinary space, the number of CSn space waits can be specified
with Wn1 and Wn0.
W31, W21, W11, W01
0
1
W30, W20, W10, W00
0
1
0
1
Description
External wait input disabled without wait
External wait input enabled with one wait
External wait input enabled with two waits
Complies with the long wait specification of
bus control register 1, 3 (BCR1, BCR3).
External wait input is enabled (Initial value)
• When CS3 is DRAM, the number of CAS assert cycles is specified by wait control bits W31
and W30
Bit 7: W31
0
1
Bit 6: W30
0
1
0
1
Description
1 cycle
2 cycles
3 cycles
Reserved (do not set)
When external wait mask bit A3WM in WCR2 is 0 and the number of CAS assert cycles is set
to 2 or more, external wait input is enabled.
• When CS2 or CS3 is synchronous DRAM, CAS latency is specified by wait control bits W31
and W30, and W21 and W20, respectively
W31, W21
0
1
W30, W20
0
1
0
1
Description
1 cycle
2 cycles
3 cycles
4 cycles
(Initial value)
With synchronous DRAM, external wait input is ignored regardless of any setting.
Rev. 2.00, 03/05, page 266 of 884