SH7615 Datasheet, PDF (523/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

For outputting transfer request from the SCIF, SIO, and TPU, the corresponding interrupt enable
bits must be set to output the interrupt signals. Note that transfer request signals from on-chip
peripheral modules (interrupt request signals) are sent not just to the DMAC but to the CPU as
well. When an on-chip peripheral module is specified as the transfer request source, set the
priority level values in the interrupt priority level registers (IPRC to IPRE) of the interrupt
controller (INTC) at or below the levels set in the I3 to I0 bits of the CPU’s status register so that
the CPU does not accept the interrupt request signal.
With the DMA transfer request signals in table 11.6, when DMA transfer is performed a DMA
transfer request (interrupt request) from any module will be cleared at the first transfer.
11.3.3 Channel Priorities
When the DMAC receives simultaneous transfer requests on two channels, it selects a channel
according to a predetermined priority order. There is a choice of two priority modes, fixed or
round-robin. The mode is selected by the priority bit, PR, in the DMA operation register
(DMAOR).
Fixed Priority Mode: In this mode, the relative channel priority levels are fixed. When PR is set
to 0, channel 0 has higher priority than channel 1. Figure 11.3 shows an example of a transfer in
burst mode.
DREQ0
DREQ1
Bus
cycle
CPU
CPU
Channel 0
destination
Channel 0
destination
Channel 1
destination
CPU
Channel 0
source
Channel 0
source
Channel 1
source
Figure 11.3 Fixed Mode DMA Transfer in Burst Mode
(Dual Address, DREQn Falling-Edge Detection)
In cycle-steal mode, once a channel 0 request is accepted, channel 1 requests are also accepted
until the next request is accepted, which makes more effective use of the bus cycle. If requests
come simultaneously for channel 0 and channel 1 when DMA operation is starting, the first is
transmitted with channel 0, and thereafter channel 1 and channel 0 transfers are performed
alternately.
Rev. 2.00, 03/05, page 485 of 884