SH7615 Datasheet, PDF (289/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Section 7 Bus State Controller (BSC)
7.1 Overview
The bus state controller (BSC) manages the address spaces and outputs control signals to allow
optimum memory accesses to the five spaces. This enables memories like DRAM, and SDRAM,
and peripheral chips, to be linked directly.
7.1.1 Features
The BSC has the following features:
• Address space is managed as five spaces
 Maximum linear 32 Mbytes for each of the address spaces CS0 to CS4
 Memory type (DRAM, synchronous DRAM, burst ROM, etc.) can be specified for each
space.
 Bus width (8, 16, or 32 bits) can be selected for each space.
 Wait state insertion can be controlled for each space.
 Control signals are output for each space.
• Cache
 Cache area and cache-through area can be selected by access address.
 In cache access, in the event of a cache access miss 16 bytes are read consecutively in 4-
byte units to fill the cache. Write-through mode/write-back mode can be selected for
writes.
 In cache-through access, access is performed according to access size.
• Refresh
 Supports CAS-before-RAS refresh (auto-refresh) and self-refresh.
 Refresh interval can be set by the refresh counter and clock selection.
 Intensive refreshing by means of refresh count setting (1, 2, 4, 6, or 8)
• Direct interface to DRAM
 Row/column address multiplex output.
 Burst transfer during reads, fast page mode for consecutive accesses.
 TP cycle generation to secure RAS precharge time.
 EDO mode
• Direct interface to synchronous DRAM
 Row/column address multiplex output.
 Selection of burst read, single write mode or burst read, burst write mode
 Bank active mode
Rev. 2.00, 03/05, page 251 of 884