SH7615 Datasheet, PDF (718/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

16.2.5 Timer Status Register (TSR)
Channel 0: TSR0
Bit: 7
6
5
4
3
2
1
0
—
—
—
TCFV TGFD TGFC TGFB TGFA
Initial value: 1
1
0
0
0
0
0
0
R/W: R
R
R R/(W)^* R/(W)^* R/(W)^* R/(W)^* R/(W)^*
Note: * Only 0 can be written, to clear the flags.
Channel 1: TSR1
Channel 2: TSR2
Bit:
Initial value:
R/W:
7
TCFD
1
R
6
5
4
3
— TCFU TCFV —
1
0
0
0
R R/(W)^* R/(W)^* R
Note: * Only 0 can be written, to clear the flags.
2
1
0
— TGFB TGFA
0
0
0
R R/(W)^* R/(W)^*
The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has three
TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset.
Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts
in channels 1, and 2.
In channel 0, bit 7 is reserved. It is always read as 1 and cannot be modified.
Bit 7: TCFD
0
1
Description
TCNT counts down
TCNT counts up
(Initial value)
Bit 6—Reserved: This bit is always read as 1. The write value should always be 1.
Rev. 2.00, 03/05, page 680 of 884