SH7615 Datasheet, PDF (760/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Contention between TCNT Write and Increment Operations: If incrementing occurs in the T₂
state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.
Figure 16.46 shows the timing in this case.
TCNT write cycle
T₁
T₂
Pφ
Address
TCNT address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 16.46 Contention between TCNT Write and Increment Operations
Rev. 2.00, 03/05, page 722 of 884