SH7615 Datasheet, PDF (475/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

10.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)
TRSCER specifies whether or not multicast address frame receive status information reported by
bit 7 in the EtherC/E-DMAC status register (EESR) is to be indicated in the corresponding
descriptor. Bit 7 in TRSCER corresponds to bit 7 of EESR. When bit 7 is set to 0, the receive
status (bit 7 of EESR) is indicated in the RFE bit of the receive descriptor. When the bit is set to 1,
the occurrence of the corresponding source is not indicated in the descriptor. After the chip is
reset, the bit is cleared to 0.
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
RMAFCE —
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W
R
R
R
R
R
R
R
Bits 31 to 8—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 7—Multicast Address Frame Receive (RMAF) Bit Copy Enable (RMAFCE)
Bit 7: RMAFCE
0
1
Description
Enables the RMAF bit status to be indicated in the RFS7 bit in the receive
descriptor.
Disables occurrence of corresponding source to be indicated in the RFS7 bit in
the receive descriptor.
Bits 6 to 0—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 2.00, 03/05, page 437 of 884