SH7615 Datasheet, PDF (827/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

7. When the internal clock stabilizes, the CKPACK pin goes high, giving external notification
that the chip can be operated.
The standby state, all on-chip peripheral module states, and all pin states during clock pause are
the same as in the normal standby mode. Figure 20.2 shows the timing chart for the clock pause
function.
CKIO input
CKPREQ/CKM
input
CKPACK
output
Frequency
modification
Clock pause request
cancellation
WDT count-up Normal state
Clock pause
acceptance
processing
Clock pause state
Figure 20.2 Clock Pause Function Timing Chart (PLL Circuit 1 Operating)
Figure 20.3 shows the clock pause function timing chart when the PLL circuit is halted.
Frequency
modification
CKIO input
CKPREQ/
CKM input
CKPACK
output
Clock pause request
cancellation
Clock pause
acceptance
processing
Clock pause state
Normal state
Figure 20.3 Clock Pause Function Timing Chart (PLL Circuit 1 Halted)
Rev. 2.00, 03/05, page 789 of 884