SH7615 Datasheet, PDF (16/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Item
Page Revisions (See Manual for Details)
10.3.1 Descriptor List
and Data Buffers
449 Transmit Descriptor
Notes replaced
Notes: 1. The descriptor start address must be specified to
align with an address boundary corresponding to the
descriptor length specified in the E-DMAC mode register
(EDMR).
2. The transmit buffer start address must be specified to align
with a longword boundary. Note, however, that it must be
aligned with a 16-byte boundary when SDRAM is connected.
Transmit Descriptor 0
(TD0)
451 Bit 27—Transmit Frame Error (TFE)
Description deleted
Indicates that one or other bit of the transmit frame status
indicated by bits 26 to 0 is set. ...
Bits 26 to 0—Transmit Frame Status 26 to 0 (TFS26 to TFS0)
• Descriptions of TFS26 to TFS5 replaced
• Description of TFS1 amended
Delayed Collision Detect in Transmission (corresponds to
CD bit in EESR)
Transmit Descriptor 2
(TD2)
452 Note replaced
Receive Descriptor
Notes replaced
454 Bit 27—Receive Frame Error (RFE)
Description amended
... indicated by bits 26 to 0 is set. Whether or not the multicast
address frame receive information, which is part of the receive
frame status, is copied into this bit is specified by the
transmit/receive status copy enable register.
Bits 26 to 0—Receive Frame Status 26 to 0 (RFS26 to RFS0)
Description of RFS8 amended
Receive Descriptor 2
(RD2)
455 Note replaced
10.4 Usage Notes
461 Newly added
11.2.4 DMA Channel 473
Control Registers 0 and 1
(CHCR0, CHCR1)
Bit 4—Transfer Bus Mode
Bit (TB)
Description amended
When 1 (burst mode) is set to bit TB, set 1 (edge detection) to
the DREQ select bit (DS).
11.5 Usage Notes
520 to Notes 12, 13, 14, 15, and 16 added
524
Rev. 2.00, 03/05, page xvi of xxxviii