SH7615 Datasheet, PDF (765/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Contention between Buffer Register Write and Input Capture: If the input capture signal is
generated in the T₂ state of a buffer register write cycle, the buffer operation takes precedence and
the write to the buffer register is not performed.
Figure 16.51 shows the timing in this case.
Pφ
Address
Write signal
Input capture
signal
TCNT
Buffer register write cycle
T₁
T₂
Buffer register
address
N
TGR
M
N
Buffer
M
register
Figure 16.51 Contention between Buffer Register Write and Input Capture
Rev. 2.00, 03/05, page 727 of 884