SH7615 Datasheet, PDF (424/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 0: ICD
Description
0
PHY-LSI has not detected an illegal carrier on the line
(Initial value)
1
PHY-LSI has detected an illegal carrier on the line
Note: If a change in the signal input from the PHY-LSI occurs before the software recognition
period, the correct information may not be obtained. Refer to the timing specification for the
PHY-LSI used.
9.2.3 EtherC Interrupt Permission Register (ECSIPR)
Bit: 31
30
29
...
11
10
9
8
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
— LCHNGI MPDIP ICDIP
P
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R/W R/W R/W
This register enables or disables the interrupt sources indicated by the EtherC status register. Each
bit in this register enables or disables the interrupt indicated by the corresponding bit in the EtherC
status register.
Bits 31 to 3—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 2— LINK Signal Changed Interrupt Permission (LCHNGIP): Controls interrupt notification
by the LINK Signal Changed bit.
Bit 2: LCHNGIP
0
1
Description
Interrupt notification by LCHNG bit in ECSR is disabled
Interrupt notification by LCHNG bit in ECSR is enabled
(Initial value)
Bit 1—Magic Packet Detection Interrupt Permission (MPDIP): Controls interrupt notification by
the Magic Packet Detection bit.
Bit 1: MPDIP
0
1
Description
Interrupt notification by MPD bit in ECSR is disabled
Interrupt notification by MPD bit in ECSR is enabled
(Initial value)
Rev. 2.00, 03/05, page 386 of 884