SH7615 Datasheet, PDF (68/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

• Sleep Mode
A transition to sleep mode is made if the SLEEP instruction is executed while the standby bit
(SBY) is cleared to 0 in standby control register 1 (SBYCR1). In sleep mode CPU operations
stop but data in the CPU’s internal registers and in on-chip cache memory and on-chip RAM is
retained. The functions of the on-chip supporting modules do not stop.
• Standby Mode
A transition to standby mode is made if the SLEEP instruction is executed while SBY is set to
1 in SBYCR1. In standby mode the CPU, the on-chip modules, and the oscillator all stop.
When entering standby mode, the DMAC’s DMA master enable bit should be cleared to 0.
Also, the cache should be turned off before entering this mode. The contents of the cache and
on-chip RAM are not retained in this mode.
Standby mode is exited by means of a reset or an external NMI interrupt. When standby mode
is exited, the normal program execution state is entered via the exception handling state after
the elapse of the oscillation settling time.
If a transition is made to standby mode using the clock pause function, it is possible to change
the frequency of the CKIO pin input clock, or to stop the clock itself. When SBY in SBYCR1
is set to 1 and a low level is applied to the CKPREQ/CKM pin, a transition is made to standby
mode and a low level is output from the CKPACK pin. The clock can then be stopped, or its
frequency changed.
On-chip supporting module states and pin states are the same as in the normal standby mode
entered by means of the SLEEP instruction. A transition to the program execution state is
made by applying a high level to the CKPREQ/CKM pin.
In this mode the oscillator is halted, greatly reducing power consumption.
• Module Standby Function
A module standby function is provided for the following on-chip supporting modules: the
direct memory access controller (DMAC), DSP, 16-bit free-running timer (FRT), serial
communication interface with FIFO (SCIF), serial I/O (SIO), user break controller (UBC), and
timer pulse unit (TPU). A module standby function is not supported for the Ethernet controller
(EtherC) or the Ethernet direct memory access controller (E-DMAC).
Setting one of module stop bits 11 to 3 and 1 (MSTP11 to MSTP3, MSTP1) to 1 in the standby
control register (SBYCR1/2) stops the clock supply to the corresponding on-chip supporting
module. Use of this function enables power consumption to be reduced.
The module standby function is cleared by clearing the corresponding MSTP bit to 0.
DSP instructions must not be used when the DSP has been placed in the module standby state.
When using the DMAC module standby function, the direct memory access controller’s DMA
master enable bit should be cleared to 0.
Rev. 2.00, 03/05, page 30 of 884