SH7615 Datasheet, PDF (485/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

10.2.16 Transmission-Buffer Read Address Register (TBRAR)
This is the register for storing the buffer address to be read in the transmission buffer when the E-
DMAC reads data from the transmission buffer. Which addresses in the transmission buffer are
processed by the E-DMAC can be recognized by monitoring addresses displayed in this register.
Bit: 31
30
29
28
27
26
25
24
TBRA31 TBRA30 TBRA29 TBRA28 TBRA27 TBRA26 TBRA25 TBRA24
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 23
22
21
20
19
18
17
16
TBRA23 TBRA22 TBRA21 TBRA20 TBRA19 TBRA18 TBRA17 TBRA16
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 15
14
13
12
11
10
9
TBRA15 TBRA14 TBRA13 TBRA12 TBRA11 TBRA10 TBRA9
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
TBRA8
0
R
Bit:
Initial value:
R/W:
7
TBRA7
0
R
6
TBRA6
0
R
5
TBRA5
0
R
4
TBRA4
0
R
3
TBRA3
0
R
2
TBRA2
0
R
1
TBRA1
0
R
0
TBRA0
0
R
Bits 31 to 0—Transmission-buffer read address (TBRD): This bit can only be read. Writing is
disabled.
Note: The buffer read processing result from the E-DMAC and the value read by the register
may not be the same.
Rev. 2.00, 03/05, page 447 of 884