SH7615 Datasheet, PDF (612/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-FIFO-data-empty interrupt
(TXI) request generation when, after serial transmit data is transferred from the transmit FIFO data
register (SCFTDR) to the transmit shift register (SCTSR), the number of data bytes in SCFTDR
falls to or below the transmit trigger set number, and the TDFE flag is set to 1 in the serial status 1
register (SC1SSR).
Bit 7: TIE
Description
0
Transmit-FIFO-data-empty interrupt (TXI) request disabled^* (Initial value)
1
Transmit-FIFO-data-empty interrupt (TXI) request enabled
Note: * TXI interrupt requests can be cleared by writing transmit data exceeding the transmit
trigger set number to SCFTDR, reading 1 from the TDFE flag, then clearing it to 0, or by
clearing the TIE bit to 0. When transmit data is written to SCFTDR using the on-chip
DMAC, the TDFE flag is cleared automatically.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables generation of receive-FIFO-data full
interrupt (RXI), receive-error interrupt (ERI), and break interrupt (BRI) requests when, after serial
receive data is transferred from the receive shift register (SCRSR) to the receive FIFO data
register (SCFRDR), the number of data bytes in SCFRDR reaches or exceeds the receive trigger
set number, and the RDF flag is set to 1 in SC1SSR.
Bit 6: RIE
Description
0
Receive-FIFO-data-full interrupt (RXI) request, receive-error interrupt (ERI)
request, and break interrupt (BRI) request disabled^*
(Initial value)
1
Receive-FIFO-data-full interrupt (RXI) request, receive-error interrupt (ERI)
request, and break interrupt (BRI) request enabled^*
Note: * RXI, ERI, and BRI interrupt requests can be cleared by reading 1 from the RDF or DR
flag, the FER, PER, ORER, or ER flag, or the BRK flag, then clearing the flag to 0, or by
clearing the RIE bit to 0. With the RDF flag, read receive data from SCFRDR until the
number of receive data bytes is less than the receive trigger set number, then read 1
from the RDF flag and clear it to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCIF.
Bit 5: TE
Description
0
Transmission disabled^*1
1
Transmission enabled^*2
(Initial value)
Notes: 1. The TDRE flag in SC1SSR is fixed at 1.
2. Serial transmission is started when transmit data is written to SCFTDR in this state.
Serial mode register (SCSMR) and FIFO control register (SCFCR) settings must be
made, the transmission format decided, and the transmit FIFO reset, before the TE bit
is set to 1.
Rev. 2.00, 03/05, page 574 of 884