SH7615 Datasheet, PDF (377/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

CKIO
Tr Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 Tc1 Tc2 (Tpc)
A24–A16
Row address
A15–A1
RD/WR
RAS
Row
address
Column address Column address Column address Column address
CASn
Read
D15–D0
CAS/OE
Write
D15–D0
CAS/OE
High
DACKn*
Note: * DACKn waveform when active-low is specified
Figure 7.49 DRAM EDO Mode Burst Access Timing
7.6.7 DRAM Single Transfer
Wait states equivalent to the value set in bits DSWW1 and DSWW0 in BCR3 can be inserted
between DACKn assertion and CASn assertion in a write in DMA single address transfer mode.
Inserting wait states allows the data setup time for external device memory. Figure 7.50 shows the
write cycle timing in DMA single transfer mode when DSWW1/DSWW0 = 01 and RASD = 1.
The DMA single transfer mode read cycle is the same as a CPU or DMA dual transfer mode read
cycle.
Rev. 2.00, 03/05, page 339 of 884