SH7615 Datasheet, PDF (214/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

5.3.19 Vector Number Setting Register M (VCRM)
Vector number setting register M (VCRM) is a 16-bit read/write register that sets the serial
communication interface with FIFO 1 (SCIF1) break interrupt and transmit-data-empty interrupt
vector numbers (0 to 127).
VCRM is initialized to H'0000 by a reset. It is not initialized in standby mode.
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
— SBR1V6 SBR1V5 SBR1V4 SBR1V3 SBR1V2 SBR1V1 SBR1V0
0
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
— STX1V6 STX1V5 STX1V4 STX1V3 STX1V2 STX1V1 STX1V0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W R/W R/W R/W R/W R/W
Bits 15 and 7—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 14 to 8—Serial Communication Interface with FIFO 1 (SCIF1) Break Interrupt Vector
Number 6 to 0 (SBR1V6 to SBR1V0): These bits set the vector number for the serial
communication interface with FIFO 1 (SCIF1) break interrupt. There are seven bits, so the value
can be set between 0 and 127.
Bits 6 to 0—Serial Communication Interface with FIFO 1 (SCIF1) Transmit-Data-Empty Interrupt
Vector Number 6 to 0 (STE1V6 to STE1V0): These bits set the vector number for the serial
communication interface with FIFO 1 (SCIF1) transmit-data-empty interrupt. There are seven bits,
so the value can be set between 0 and 127.
Rev. 2.00, 03/05, page 176 of 884