SH7615 Datasheet, PDF (281/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Exec: branch Dest
Dest: instr; Not executed
Interrupt
Int: interrupt routine
Figure 6.2 When Interrupt Occurs before Branch Instruction Is Executed
Table 6.3 BSA Values Stored in Exception Handling before Execution of Branch
Destination Instruction
Branch
Delay
No delay
Branch Destination
(Dest)
4n
4n + 2
4n or 4n + 2
BSA
4n
4n + 2
4n
Branch Source Address Calculable by Means
of BRSR and BRFR
Exec = IA = BSA – 2 × PID
Dest = BSA
Exec = IA = BSA – 2 × PID
If PID is an odd number, the value incremented by 2 indicates the instruction buffer, but the
equations in the table do not take this into account. Therefore, the calculation can be performed
using the values of BSA stored in BRSR and PID stored in BRFR.
3. The location indicated by the address before branch occurrence, IA, differs according to the
kind of branch.
a. Branch instruction: Branch instruction address
b. Repeat loop: 2nd instruction from last in repeat loop
Repeat_Start: inst (1); → BRDR
inst(2);
:
inst (n-1); → Address calculated from BRSR and BRFR
Repeat End: inst (n);
c. Interrupt: Instruction executed immediately before interrupt
The address of the first instruction in the interrupt routine is stored in BRDR.
In a repeat loop consisting of no more than three instructions, an instruction fetch cycle is not
generated. As the branch destination address is unknown, a PC trace cannot be performed.
Rev. 2.00, 03/05, page 243 of 884