SH7615 Datasheet, PDF (759/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in
the final state in which it matches the TGR value (the point at which the count value matched by
TCNT is updated). Consequently, the actual counter frequency is given by the following formula:
f = ^Pφ
(N + 1)
Where
f : Counter frequency
Pφ : Peripheral module clock
N : TGR set value
Contention between TCNT Write and Clear Operations: If the counter clear signal is
generated in the T₂ state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT
write is not performed.
Figure 16.45 shows the timing in this case.
TCNT write cycle
T₁
T₂
Pφ
Address
TCNT address
Write signal
Counter clear
signal
TCNT
N
H'0000
Figure 16.45 Contention between TCNT Write and Clear Operations
Rev. 2.00, 03/05, page 721 of 884