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SH7615 Datasheet, PDF (290/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7600 Series
• Bus arbitration
 All resources are shared with the CPU, and use of the bus is granted on reception of a bus
release request from off-chip.
• Refresh counter can be used as an interval timer
 Interrupt request generation on compare match (CMI interrupt request signal).
Rev. 2.00, 03/05, page 252 of 884