SH7615 Datasheet, PDF (239/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Section 6 User Break Controller (UBC)
6.1 Overview
The user break controller (UBC) provides functions that simplify program debugging. When break
conditions are set in the UBC, a user break interrupt is generated according to the conditions of the
bus cycle generated by the CPU or on-chip DMAC (DMAC or E-DMAC).
This function makes it easy to design a sophisticated self-monitoring debugger, enabling programs
to be debugged with the chip alone, without using an in-circuit emulator.
6.1.1 Features
The UBC has the following features:
• The following can be set as break conditions:
 Number of break channels: Four (channels A, B, C, and D)
User break interrupts can be generated on independent or sequential conditions for
channels A, B, C, and D.
 Sequential break settings
• Channel A → channel B → channel C → channel D
• Channel B → channel C → channel D
• Channel C → channel D
1. Address: 32-bit masking capability, individual address setting possible (cache bus (CPU),
internal bus (DMAC, E-DMAC), X/Y bus)
2. Data (channels C and D only,): 32-bit masking capability, individual address setting
possible (cache bus (CPU), internal bus (DMAC, E-DMAC), X/Y bus)
3. Bus master: CPU cycle/on-chip DMAC (DMAC, E-DMAC) cycle
4. Bus cycle: Instruction fetch/data access
5. Read/write
6. Operand cycle: Byte/word/longword
• User break interrupt generation on occurrence of break condition
A user-written user break interrupt exception routine can be executed.
• Processing can be stopped before or after instruction execution in an instruction fetch cycle.
• Break with specification of number of executions (channels C and D only)
Settable number of executions: maximum 2¹² – 1 (4095)
• PC trace function
The branch source/branch destination can be traced when a branch instruction is fetched
(maximum 8 addresses (4 pairs)).
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