SH7615 Datasheet, PDF (124/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Instruction
LDS.L @Rm+,X1
LDS.L @Rm+,Y0
LDS.L @Rm+,Y1
NOP
RTE
SETRC Rm
SETRC #imm
SETT
SLEEP
STC SR,Rn
STC GBR,Rn
STC VBR,Rn
STC MOD,Rn
STC RE,Rn
STC RS,Rn
STC.L SR,@–Rn
STC.L GBR,@–Rn
STC.L VBR,@–Rn
STC.L MOD,@–Rn
STC.L RE,@–Rn
STC.L RS,@–Rn
STS MACH,Rn
STS MACL,Rn
STS PR,Rn
STS DSR,Rn
STS A0,Rn
STS X0,Rn
STS X1,Rn
STS Y0,Rn
STS Y1,Rn
Instruction Code
0100mmmm10010110
0100mmmm10100110
0100mmmm10110110
0000000000001001
0000000000101011
0100mmmm00010100
10000010iiiiiiii
0000000000011000
0000000000011011
0000nnnn00000010
0000nnnn00010010
0000nnnn00100010
0000nnnn01010010
0000nnnn01110010
0000nnnn01100010
0100nnnn00000011
0100nnnn00010011
0100nnnn00100011
0100nnnn01010011
0100nnnn01110011
0100nnnn01100011
0000nnnn00001010
0000nnnn00011010
0000nnnn00101010
0000nnnn01101010
0000nnnn01111010
0000nnnn10001010
0000nnnn10011010
0000nnnn10101010
0000nnnn10111010
Operation
(Rm) → X1, Rm + 4 → Rm
(Rm) → Y0, Rm + 4 → Rm
(Rm) → Y1, Rm + 4 → Rm
No operation
Delayed branch,
stack area → PC/SR
RE–RS operation result
(repeat status) → RF1, RF0
Rm[11:0] → RC (SR[27:16])
RE–RS operation result
(repeat status) → RF1, RF0
imm → RC (SR[23:16]),
0 → SR[27:24]
1→T
Sleep
SR → Rn
GBR → Rn
VBR → Rn
MOD → Rn
RE → Rn
RS → Rn
Rn–4 → Rn, SR → (Rn)
Rn–4 → Rn, GBR → (Rn)
Rn–4 → Rn, VBR → (Rn)
Rn–4 → Rn, MOD → (Rn)
Rn–4 → Rn, RE → (Rn)
Rn–4 → Rn, RS → (Rn)
MACH → Rn
MACL → Rn
PR → Rn
DSR → Rn
A0 → Rn
X0 → Rn
X1 → Rn
Y0 → Rn
Y1 → Rn
Cycles
1
1
1
1
4
T Bit
—
—
—
—
LSB
1
—
1
1
1
1
3^*
—
1
—
1
—
1
—
1
—
1
—
1
—
2
—
2
—
2
—
2
—
2
—
2
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
1
—
Rev. 2.00, 03/05, page 86 of 884