SH7615 Datasheet, PDF (186/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

5.2.5 IRQ Interrupts
An IRQ interrupt is requested when the external interrupt vector mode select bit (EXIMD) of the
interrupt control register (ICR) is set to 1. An IRQ interrupt corresponds to input at one of pins
IRL3 to IRL0. Low-level sensing or rising/falling/both-edge sensing can be selected
independently for each pin by the IRQ sense select bits (IRQ31S to IRQ00S) in the IRQ
control/status register (IRQCSR), and a priority level of 0 to 15 can be selected independently for
each pin by means of interrupt priority register C (IPRC). Set the interrupt vector mode select bit
(VECMD) of the interrupt control register (ICR) to enable external input of vector numbers.
External vector numbers are 0 to 127, and are input to the external vector input pins (D7 to D0)
during the interrupt vector fetch bus cycle. When an external vector is used, 0 is input to D7.
When an IRQ interrupt is accepted in external vector mode, the IRQ interrupt priority level is
output from the interrupt acceptance level output pins (A3 to A0). The external vector fetch signal
(IVECF) is also asserted. The external vector number is read from signals D7 to D0 at this time.
IRQ interrupt exception processing sets the interrupt mask bits (I3 to I0) in the status register (SR)
to the priority level value of the IRQ interrupt that was accepted.
Table 5.3 IRL Interrupt Priority Levels and Auto-Vector Numbers
IRL3
0
1
IRL2
0
1
0
1
Pin
IRL1
0
1
0
1
0
1
0
1
IRL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Priority
Level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Vector
Number
71
70
69
68
67
66
65
64
Rev. 2.00, 03/05, page 148 of 884