SH7615 Datasheet, PDF (394/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

• High-impedance conditions: Not dependent on BCR settings etc. when WAIT = L and
BUSHiZ = L
• Applicable pins: A[24:0], D[31:0], CS3, RD/WR, RD, RAS, CAS/OE, DQMLL/WE0,
DQMLU/WE1, DQMUL/WE2, DQMUU/WE3 (total of 66 pins)
CKIO
WAIT
BUSHiZ
Target pins
Period
Figure 7.60 BUSHiZ Bus Timing
1. Can be used when memory is shared by the CPU and an external device.
2. When BUSHiZ is asserted after asserting WAIT, the CPU appears to release the bus.
3. When it becomes possible to access the shared memory, BUSHiZ is negated.
4. When the data is ready, WAIT is negated.
This procedure allows the CPU and an external device to share memory.
7.11 Usage Notes
7.11.1 Normal Space Access after Synchronous DRAM Write when Using DMAC
Negation of the DQMn/WEn signal in a synchronous DRAM write and CSn assertion in an
immediately following normal space access both occur at the same rising edge of CKIO (figure
7.61). As there is a risk of an erroneous write to normal space in this case, when synchronous
DRAM or a high-speed device is connected to normal space, it is recommended that CSn be
delayed on the system side.
Cases in which a synchronous DRAM write and normal space access occur consecutively are
shown in table 7.10.
Table 7.10 Access Sequence
Write to Synchronous DRAM
Normal Space Access
CPU
DMA
DMA
CPU
DMA
DMA
Note: When an access by the CPU is performed immediately after a write by the CPU, internally
the accesses are not consecutive.
Rev. 2.00, 03/05, page 356 of 884