SH7615 Datasheet, PDF (250/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bits 5 and 4—Instruction Fetch/Data Access Select B (IDB1, IDB0): These bits specify whether
an instruction fetch cycle or data access cycle is to be selected as the bus cycle used as a channel B
break condition.
Bit 5:
IDB1
0
1
Bit 4:
IDB0
0
1
0
1
Description
Channel B user break interrupt is not generated
(Initial value)
Instruction fetch cycle is selected as break condition
Data access cycle is selected as break condition
Instruction fetch cycle or data access cycle is selected as break condition
Bits 3 and 2—Read/Write Select B (RWB1, RWB0): These bits specify whether a read cycle or
write cycle is to be selected as the bus cycle used as a channel B break condition.
Bit 3:
RWB1
0
1
Bit 2:
RWB0
0
1
0
1
Description
Channel B user break interrupt is not generated
Read cycle is selected as break condition
Write cycle is selected as break condition
Read cycle or write cycle is selected as break condition
(Initial value)
Bits 1 and 0—Operand Size Select B (SZB1, SZB0): These bits select the operand size of the bus
cycle used as a channel B break condition.
Bit 1:
SZB1
Bit 0:
SZB0
Description
0
0
Operand size is not included in break conditions
(Initial value)
1
Byte access is selected as break condition
1
0
Word access is selected as break condition
1
Longword access is selected as break condition
Notes: When a break is to be executed on an instruction fetch, clear the SZB0 bit to 0. All
instructions are regarded as being accessed using word size (instruction fetches are always
performed as longword).
In the case of an instruction, the operand size is word; in the case of a CPU/DMAC, E-
DMAC data access, it is determined by the specified operand size. Note that the operand
size is not determined by the bus width of the space accessed.
Rev. 2.00, 03/05, page 212 of 884