SH7615 Datasheet, PDF (762/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T₂ state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
write data.
Figure 16.48 shows the timing in this case.
TGR write cycle
T₁
T₂
Pφ
Address
Buffer register
address
Write signal
Compare
match signal
Buffer
register
Buffer register write data
N
M
TGR
M
Figure 16.48 Contention between Buffer Register Write and Compare Match
Rev. 2.00, 03/05, page 724 of 884