SH7615 Datasheet, PDF (28/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

5.4.1 Interrupt Sequence ............................................................................................... 191
5.4.2 Stack State after Interrupt Exception Handling ................................................... 193
5.5 Interrupt Response Time................................................................................................... 193
5.6 Sampling of Pins IRL3 to IRL0 ........................................................................................ 195
5.7 Usage Notes ...................................................................................................................... 196
Section 6 User Break Controller (UBC) ....................................................................... 201
6.1 Overview........................................................................................................................... 201
6.1.1 Features................................................................................................................ 201
6.1.2 Block Diagram..................................................................................................... 202
6.1.3 Register Configuration......................................................................................... 203
6.2 Register Descriptions........................................................................................................ 205
6.2.1 Break Address Register A (BARA) ..................................................................... 205
6.2.2 Break Address Mask Register A (BAMRA)........................................................ 206
6.2.3 Break Bus Cycle Register A (BBRA).................................................................. 207
6.2.4 Break Address Register B (BARB) ..................................................................... 209
6.2.5 Break Address Mask Register B (BAMRB) ........................................................ 210
6.2.6 Break Bus Cycle Register B (BBRB) .................................................................. 211
6.2.7 Break Address Register C (BARC) ..................................................................... 213
6.2.8 Break Address Mask Register C (BAMRC) ........................................................ 214
6.2.9 Break Data Register C (BDRC)........................................................................... 216
6.2.10 Break Data Mask Register C (BDMRC) ............................................................. 217
6.2.11 Break Bus Cycle Register C (BBRC) .................................................................. 219
6.2.12 Break Execution Times Register C (BETRC) ..................................................... 220
6.2.13 Break Address Register D (BARD)..................................................................... 221
6.2.14 Break Address Mask Register D (BAMRD)........................................................ 222
6.2.15 Break Data Register D (BDRD) .......................................................................... 224
6.2.16 Break Data Mask Register D (BDMRD) ............................................................. 225
6.2.17 Break Bus Cycle Register D (BBRD).................................................................. 227
6.2.18 Break Execution Times Register D (BETRD)..................................................... 228
6.2.19 Break Control Register (BRCR) .......................................................................... 229
6.2.20 Branch Flag Registers (BRFR) ............................................................................ 234
6.2.21 Branch Source Registers (BRSR) ........................................................................ 235
6.2.22 Branch Destination Registers (BRDR) ................................................................ 236
6.3 Operation .......................................................................................................................... 237
6.3.1 User Break Operation Sequence .......................................................................... 237
6.3.2 Instruction Fetch Cycle Break ............................................................................. 238
6.3.3 Data Access Cycle Break..................................................................................... 239
6.3.4 Saved Program Counter (PC) Value .................................................................... 240
6.3.5 X Memory Bus or Y Memory Bus Cycle Break.................................................. 240
6.3.6 Sequential Break.................................................................................................. 241
6.3.7 PC Traces............................................................................................................. 242
6.3.8 Examples of Use .................................................................................................. 244
Rev. 2.00, 03/05, page xxviii of xxxviii