SH7615 Datasheet, PDF (514/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 4: Bit 3: Bit 2: Bit 1: Bit 0:
RS4 RS3 RS2 RS1 RS0 Description
0
1
0
0
0
Reserved (setting prohibited)
1
SCIF channel 2 RXI (on-chip SCI with FIFO channel
2 receive-data-full interrupt request)^*1
1
0
SCIF channel 2 TXI (on-chip SCI with FIFO channel
2 transmit-data-empty interrupt request)^*1
1
Reserved (setting prohibited)
1
0
0
TPU TGI0A (on-chip TPU input capture channel 0A
interrupt request)^*1
1
TPU TGI0B (on-chip TPU input capture channel 0B
interrupt request)^*1
1
0
TPU TGI0C (on-chip TPU input capture channel 0C
interrupt request)^*1
1
TPU TGI0D (on-chip TPU input capture channel 0D
interrupt request)^*1
1
0
0
0
0
Reserved (setting prohibited)
1
SIO channel 0 RDFI (on-chip SIO channel 0
receive-data-full interrupt request)^*1
1
0
SIO channel 0 TDEI (on-chip SIO channel 0
transmit-data-empty interrupt request)^*1
1
Reserved (setting prohibited)
1
0
0
Reserved (setting prohibited)
1
SIO channel 1 RDFI (on-chip SIO channel 1
receive-data-full interrupt request)^*1
1
0
SIO channel 1 TDEI (on-chip SIO channel 1
transmit-data-empty interrupt request)^*1
1
Reserved (setting prohibited)
1
0
0
0
Reserved (setting prohibited)
1
SIO channel 2 RDFI (on-chip SIO channel 2
receive-data-full interrupt request)^*1
1
0
SIO channel 2 TDEI (on-chip SIO channel 2
transmit-data-empty interrupt request)^*1
1
Reserved (setting prohibited)
1
*
*
Reserved (setting prohibited)
Note:
* Don’t care
1. When a transfer request is generated by an on-chip module, select cycle-steal as the
bus mode, dual transfer as the transfer mode, and falling edge detection for the DREQn
setting.
Rev. 2.00, 03/05, page 476 of 884