SH7615 Datasheet, PDF (578/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

12.4.5 Input Capture Flag (ICF) Setting Timing
Input capture input sets the input capture flag (ICF) to 1 and simultaneously transfers the FRC
value to FICR. Figure 12.10 shows the timing.
Pφ
Input capture
signal
ICF
FRC
N
FICR
N
Figure 12.10 ICF Setting Timing
12.4.6 Output Compare Flag (OCFA, OCFB) Setting Timing
The compare match signal output (when OCRA or OCRB matches the FRC value) sets output
compare flag OCFA or OCFB to 1. The compare match signal is generated in the last state in
which the values matched (at the timing for updating the count value that matched the FRC). After
OCRA or OCRB matches the FRC, no compare match is generated until the next increment
occurs. Figure 12.11 shows the timing for setting OCFA and OCFB.
Rev. 2.00, 03/05, page 540 of 884