SH7615 Datasheet, PDF (491/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Receive descriptor
31 30 29 28 27 26
RD0
RFS 26 to RFS0
31
15 16
0
RD1
RBL
RDL
31
0
RD2
RBA
Padding (4 bytes)
Receive buffer
Valid receive data
Figure 10.3 Relationship between Receive Descriptor and Receive Buffer
Receive Descriptor 0 (RD0): RD0 indicates the receive frame status. The CPU and E-DMAC use
RD0 to report the frame transmission status.
Bit 31—Receive Descriptor Active (RACT): Indicates that this descriptor is active. The E-DMAC
resets this bit after receive data has been transferred to the receive buffer. On completion of
receive frame processing, the CPU sets this bit to prepare for reception.
Bit 31: RACT
0
1
Description
The receive descriptor is invalid
Indicates that the receive buffer is not ready (access disabled by E-DMAC), or
this bit has been reset by a write-back operation on termination of E-DMAC
frame transfer processing (completion or suspension of reception)
If this state is recognized in an E-DMAC descriptor read, the E-DMAC
terminates receive processing and receive operations cannot be continued
Reception can be restarted by setting RACT to 1 and executing receive
initiation.
The receive descriptor is valid
Indicates that the receive buffer is ready (access enabled) and processing for
frame transfer from the FIFO has not been executed, or that frame transfer is in
progress
When this state is recognized in an E-DMAC descriptor read, the E-DMAC
continues with the receive operation
Bit 30—Receive Descriptor List Last (RDLE): Indicates that this descriptor is the last in the
receive descriptor list. After completion of the corresponding buffer transfer, the E-DMAC
Rev. 2.00, 03/05, page 453 of 884