SH7615 Datasheet, PDF (248/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

6.2.5 Break Address Mask Register B (BAMRB)
BAMRBH
Bit: 15
14
13
12
11
10
9
8
BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
BAMRBL
Bit: 15
14
13
12
11
10
9
8
BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Break address mask register B (BAMRB) consists of two 16-bit readable/writable registers: break
address mask register BH (BAMRBH) and break address mask register BL (BAMRBL).
BAMRBH specifies which bits of the break address set in BARBH are to be masked, and
BAMRBL specifies which bits of the break address set in BARBL are to be masked. BAMRBH
and BAMRBL are initialized to H'0000 by a power-on reset; after a manual reset, their values are
undefined.
BAMRBH Bits 15 to 0—Break Address Mask B31 to B16 (BAMB31 to BAMB16): These bits
specify whether or not corresponding channel B break address bits 31 to 16 (BAB31 to BAB16)
set in BARBH are to be masked.
BAMRBL Bits 15 to 0—Break Address Mask B15 to B0 (BAMB15 to BAMB0): These bits
specify whether or not corresponding channel B break address bits 15 to 0 (BAB15 to BAB0) set
in BARBL are to be masked.
Rev. 2.00, 03/05, page 210 of 884