SH7615 Datasheet, PDF (709/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

16.2.3 Timer I/O Control Register (TIOR)
Channel 0: TIOR0H
Channel 1: TIOR1
Channel 2: TIOR2
Bit: 7
IOB3
Initial value: 0
R/W: R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
Channel 0: TIOR0L
Bit: 7
IOD3
Initial value: 0
R/W: R/W
6
IOD2
0
R/W
5
IOD1
0
R/W
4
IOD0
0
R/W
3
IOC3
0
R/W
2
IOC2
0
R/W
1
IOC1
0
R/W
0
IOC0
0
R/W
Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the
register operates as a buffer register.
The TIOR registers are 8-bit registers that control the TGR registers. The TPU has four TIOR
registers, two for channel 0 and one each for channels 1, and 2. The TIOR registers are initialized
to H'00 by a reset.
Note that TIOR is affected by the TMDR setting.
The initial output specified by TIOR becomes valid when the counter is halted (i.e. when the CST
bit is cleared to 0 in TSTR). In PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
Rev. 2.00, 03/05, page 671 of 884