SH7615 Datasheet, PDF (112/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

2.5.1 CPU Instruction Set
Table 2.19 lists the CPU instructions by classification.
Table 2.19 Classification of CPU Instructions
Operation
Classification Types Code Function
No. of
Instructions
Data transfer 5
MOV
Data transfer, immediate data transfer, peripheral 39
module data transfer, structure data transfer
MOVA Effective address transfer
MOVT T bit transfer
SWAP Swap of upper and lower bytes
XTRCT Extraction of the middle of registers connected
Arithmetic 21 ADD
Binary addition
33
operations
ADDC Binary addition with carry
ADDV Binary addition with overflow
CMP/cond Comparison
DIV1
Division
DIV0S Initialization of signed division
DIV0U Initialization of unsigned division
DMULS Signed double-length multiplication
DMULU Unsigned double-length multiplication
DT
Decrement and test
EXTS Sign extension
EXTU Zero extension
MAC
Multiply/accumulate, double-length
multiply/accumulate operation
MUL
Double-length multiply operation
MULS Signed multiplication
MULU Unsigned multiplication
NEG
Negation
NEGC Negation with borrow
SUB
Binary subtraction
SUBC Binary subtraction with borrow
SUBV Binary subtraction with underflow
Rev. 2.00, 03/05, page 74 of 884