SH7615 Datasheet, PDF (226/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 1—External Interrupt Vector Mode Select (EXIMD): This bit selects IRQ mode or IRL mode.
In IRQ mode, each of signals IRL3 to IRL0 functions as a separate interrupt source. In IRL mode,
these signals can specify interrupt priority levels 1 to 15.
Bit 1: EXIMD
0
1
Description
IRL mode
IRQ mode
(Initial value)
Bit 0—Interrupt Vector Mode Select (VECMD): This bit selects auto-vector mode or external
vector mode for IRL/IRQ interrupt vector number setting. In auto-vector mode, an internally
determined vector number is set. The IRL15 and IRL14 interrupt vector numbers are set to 71 and
the IRL1 vector number is set to 64. In external vector mode, a value between 0 and 127 can be
input as the vector number from the external vector number input pins (D7 to D0).
Bit 0: VECMD
0
1
Description
Auto vector mode, vector number automatically set internally
(Initial value)
External vector mode, vector number set by external input
5.3.29 IRQ Control/Status Register (IRQCSR)
The IRQ control/status register (IRQCSR) is a 16-bit register that sets the IRL0 to IRL3 input
signal detection mode, indicates the input signal levels at pins IRL0 to IRL3, and also indicates the
IRQ interrupt status. IRQCSR is initialized by a reset. It is not initialized in standby mode.
Bit: 15
14
13
12
11
10
9
8
IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
IRL3PS IRL2PS IRL1PS IRL0PS
Initial value: 0/1
0/1
0/1
0/1
R/W: R
R
R
R
3
IRQ3F
0
R/(W)^*
2
IRQ2F
0
R/(W)^*
1
IRQ1F
0
R/(W)^*
0
IRQ0F
0
R/(W)^*
Note: * Only 0 can be written, to clear the flag (in case of edge detection).
Rev. 2.00, 03/05, page 188 of 884