SH7615 Datasheet, PDF (381/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

When one or more wait states are set for a burst ROM access, the WAIT pin is sampled. When the
burst ROM is set and 0 specified for waits, there are 2 access cycles from the second time on.
Figure 7.55 shows the timing.
T1
Tw
T2
Tw
T2
Tw
T2
Tw
T2
8-bit bus-width longword access
T1
Tw
T2
Tw
T2
8-bit bus-width word access
T1
Tw
T2
8-bit bus-width byte access
T1
Tw
T2
Tw
T2
16-bit bus-width longword access
T1
Tw
T2
16-bit bus-width word access
T1
Tw
T2
16-bit bus-width byte access
T1
Tw
T2
32-bit bus-width longword access
T1
Tw
T2
32-bit bus-width word access
T1
Tw
T2
32-bit bus-width byte access
Figure 7.53 Data Width and Burst ROM Access (1 Wait State)
Rev. 2.00, 03/05, page 343 of 884