SH7615 Datasheet, PDF (283/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

B. Register settings: BARA = H'00027128 / BAMRA = H'00000000 / BBRA = H'005A
BARB = H'00031415 / BAMRB = H'00000000 / BBRB = H'0054
BARC = H'00037226 / BAMRC = H'00000000 / BBRC = H'0056
BDRC = H'00000000 / BDMRC = H'00000000
BARD = H'0003722E / BAMRD = H'00000000 / BBRD = H'0056
BDRD = H'00000000 / BDMRD = H'00000000
BRCR = H'00080000
Set conditions: Channels A and B independent, channel C → channel D sequential mode
Channel A: Address: H'00027128; address mask: H'00000000
Bus cycle: CPU, instruction fetch (pre-execution), write, word
Channel B: Address: H'00031415; address mask: H'00000000
Bus cycle: CPU, instruction fetch (pre-execution),
read (operand size not included in conditions)
Channel C: Address: H'00037226; address mask: H'00000000
Data:
H'00000000; data mask: H'00000000
Bus cycle: CPU, instruction fetch (pre-execution), read, word
Channel D: Address: H'0003722E; address mask: H'00000000
Data:
H'00000000; data mask: H'00000000
Bus cycle: CPU, instruction fetch (pre-execution), read, word
On channel A, a user break interrupt is not generated as an instruction fetch is not a write
cycle.
On channel B, a user break interrupt is not generated as an instruction fetch is performed on an
even address.
A user break interrupt is generated by a channel C and D sequential condition match before
execution of the instruction at address H'0003722E following execution of the instruction at
address H'00037226.
Rev. 2.00, 03/05, page 245 of 884