SH7615 Datasheet, PDF (557/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

11. The following restrictions apply when using dual address mode for 16-byte transfer in cycle-
steal mode:
a. When external request and level detection are set, do not input DREQn during cycles in
which DACKn is not active after the start of DMA transfer.
Bus cycle
DACKn
(active high)
DREQn
(active high)
CPU
CPU
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(W)
DMA
(W)
DMA
(W)
DMA
(W)
CPU
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(W)
DMA
(W)
DMA
(W)
DMA
(W)
CPU
*
DACK output in read cycle
Bus cycle
CPU
CPU
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(W)
DMA
(W)
DMA
(W)
DMA
(W)
CPU
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(R)
DMA
(W)
DMA
(W)
DMA
(W)
DMA
(W)
CPU
DACKn
(active high)
DREQn
*
(active high)
DACK output in write cycle
Note: * In addition to CPU cycles, E-DMAC cycles may be inserted in some cases.
b. When external request DREQ edge detection is set, if DREQn is input continuously the
DMAC continues to operate without insertion of a CPU cycle. (However, a CPU cycle will
begin if there is no request from DREQn.)
Rev. 2.00, 03/05, page 519 of 884