SH7615 Datasheet, PDF (34/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

12.7.1 Contention between FRC Write and Clear .......................................................... 543
12.7.2 Contention between FRC Write and Increment................................................... 544
12.7.3 Contention between OCR Write and Compare Match......................................... 545
12.7.4 Internal Clock Switching and Counter Operation................................................ 545
12.7.5 Timer Output (FTOA, FTOB) ............................................................................. 547
Section 13 Watchdog Timer (WDT).............................................................................. 549
13.1 Overview........................................................................................................................... 549
13.1.1 Features................................................................................................................ 549
13.1.2 Block Diagram..................................................................................................... 550
13.1.3 Input/Output Pin .................................................................................................. 550
13.1.4 Register Configuration......................................................................................... 551
13.2 Register Descriptions........................................................................................................ 551
13.2.1 Watchdog Timer Counter (WTCNT)................................................................... 551
13.2.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 552
13.2.3 Reset Control/Status Register (RSTCSR)............................................................ 553
13.2.4 Notes on Register Access .................................................................................... 554
13.3 Operation .......................................................................................................................... 556
13.3.1 Operation in Watchdog Timer Mode................................................................... 556
13.3.2 Operation in Interval Timer Mode....................................................................... 558
13.3.3 Operation when Standby Mode is Cleared .......................................................... 558
13.3.4 Timing of Overflow Flag (OVF) Setting ............................................................. 559
13.3.5 Timing of Watchdog Timer Overflow Flag (WOVF) Setting ............................. 559
13.4 Usage Notes ...................................................................................................................... 560
13.4.1 Contention between WTCNT Write and Increment ............................................ 560
13.4.2 Changing CKS2 to CKS0 Bit Values .................................................................. 560
13.4.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 560
13.4.4 System Reset with WDTOVF.............................................................................. 561
13.4.5 Internal Reset in Watchdog Timer Mode............................................................. 561
13.4.6 Internal Reset by Watchdog Timer (WDT) in Sleep Mode ................................. 561
Section 14 Serial Communication Interface with FIFO (SCIF) ............................ 563
14.1 Overview........................................................................................................................... 563
14.1.1 Features................................................................................................................ 563
14.1.2 Block Diagrams ................................................................................................... 565
14.1.3 Input/Output Pins................................................................................................. 566
14.1.4 Register Configuration......................................................................................... 567
14.2 Register Descriptions........................................................................................................ 568
14.2.1 Receive Shift Register (SCRSR) ......................................................................... 568
14.2.2 Receive FIFO Data Register (SCFRDR) ............................................................. 568
14.2.3 Transmit Shift Register (SCTSR) ........................................................................ 569
14.2.4 Transmit FIFO Data Register (SCFTDR)............................................................ 569
14.2.5 Serial Mode Register (SCSMR)........................................................................... 570
Rev. 2.00, 03/05, page xxxiv of xxxviii