SH7615 Datasheet, PDF (618/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 3—Framing Error (FER): Indicates a framing error in the data read from the receive FIFO data
register (SCFRDR).
Bit 3: FER
0
1
Description
There is no framing error in the receive data read from SCFRDR (Initial value)
[Clearing conditions]
• In a reset or in standby mode
• When there is no framing error in SCFRDR read data
There is a framing error in the receive data read from SCFRDR
[Setting condition]
When there is a framing error in SCFRDR read data
Bit 2—Parity Error (PER): In asynchronous mode, indicates a parity error in the data read from
the receive FIFO data register (SCFRDR).
Bit 2: PER
0
1
Description
There is no parity error in the receive data read from SCFRDR
[Clearing conditions]
• In a reset or in standby mode
• When there is no parity error in SCFRDR read data
There is a parity error in the receive data read from SCFRDR
[Setting condition]
When there is a parity error in SCFRDR read data
(Initial value)
Bit 1—Receive Data Register Full (RDF): Indicates that the received data has been transferred to
the receive FIFO data register (SCFRDR), and the number of receive data bytes in SCFRDR is
equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in the FIFO
control register (SCFCR).
Rev. 2.00, 03/05, page 580 of 884