SH7615 Datasheet, PDF (758/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

DMAC
read cycle
T₁
T₂
DMAC
write cycle
T₁
T₂
Pφ
Address
Status flag
Source address
Destination
address
Interrupt
request
signal
Figure 16.43 Timing for Status Flag Clearing by DMAC Activation
16.7 Usage Notes
Note that the kinds of operation and contention described below occur during TPU operation.
Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of
single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not
operate properly with a narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 16.44 shows the input clock
conditions in phase counting mode.
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Phase
Phase
differ-
differ-
Overlap ence Overlap ence
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 16.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Rev. 2.00, 03/05, page 720 of 884