SH7615 Datasheet, PDF (591/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bit 5—Timer Enable (TME): Enables or disables the timer.
Bit 5: TME
0
1
Description
Timer disabled: WTCNT is initialized to H'00 and count-up stops
(Initial value)
WDTOVF Timer enabled: WTCNT starts counting. A
signal or interrupt
is generated when WTCNT overflows
Bits 4 and 3—Reserved: These bits are always read as 1. The write value should always be 1.
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources for input to WTCNT. The clock signals are obtained by dividing the frequency of the
system clock (φ).
Description
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source Overflow Interval^* (φ = 60 MHz)
0
0
0
φ/4 (Initial value) 17.0 µs
1
φ/128
544 µs
1
0
φ/256
1.1 ms
1
φ/512
2.2 ms
1
0
0
φ/1024
4.4 ms
1
φ/2048
8.7 ms
1
0
φ/8192
34.8 ms
1
φ/16384
69.6 ms
Note: * The overflow interval listed is the time from when the WTCNT begins counting at H'00
until an overflow occurs.
13.2.3 Reset Control/Status Register (RSTCSR)
Bit: 7
6
5
4
3
2
1
0
WOVF RSTE RSTS —
—
—
—
—
Initial value: 0
0
0
1
1
1
1
0
R/W: R/(W)^* R/W R/W
R
R
R
R
R
Note: * Only 0 can be written in bit 7, to clear the flag.
RSTCSR is an 8-bit read/write register that controls output of the reset signal generated by
watchdog timer counter (WTCNT) overflow and selects the internal reset signal type. The method
of writing to RSTCSR differs from that of most other registers to prevent inadvertent rewriting.
See section 13.2.4, Notes on Register Access, for details. RSTCR is initialized to H'1E by input of
Rev. 2.00, 03/05, page 553 of 884