SH7615 Datasheet, PDF (818/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Table 20.1 Power-Down Modes
State
Mode
On-Chip
Oscilla-
tion
Circuit,
Transition E-DMAC, CPU,
Condition EtherC Cache DSP
BSC
UBC, DMAC,
FRT,
SCIF1 to
SCIF2,
TPU, SIO2 to
SIO0
Pins
Canceling
Procedure
Sleep
mode
SLEEP Runs
instruction
executed
with SBY
bit set to 0
in SBYCR1
Halted Halted Runs Runs
Runs
1. Interrupt
2. DMA
address
error
3. Power-on
reset
4. Manual
reset
Standby SLEEP Halted
mode instruction
executed
with SBY
bit set to 1
in SBYCR1
Halted Halted
Halted, UBC: Halted, Held or 1. NMI
and and register high
interrupt
register values held
values _{Other than}
held _{UBC: Halted}
impedance _{2. Power-on}
reset
3. Manual
reset
Module MSTP bit Runs
standby for relevant
function module is
set to 1
Runs
When Runs
MSTP
is 1,
the clock
supply is
halted
When an
MSTP bit is
1, the clock
supply to
the relevant
module is
halted
FRT, and 1. Clear
SCIF1, 2
MSTP bit
pins are
to 0
initialized, _{2. Power-on}
and others _reset
operate
3. Manual
reset
20.1.2 Register
Table 20.2 shows the register configuration.
Table 20.2 Register Configuration
Name
Standby control register 1
Standby control register 2
Abbreviation R/W
SBYCR1
R/W
SBYCR2
R/W
Initial Value
H'00
H'00
Address
H'FFFFFE91
H'FFFFFE93
Access Size
8
8
Rev. 2.00, 03/05, page 780 of 884