SH7615 Datasheet, PDF (750/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
TPU has 8 input capture/compare match interrupts, four for channel 0, and two each for channels
1, and 2.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a particular channel. The
interrupt request is cleared by clearing the TCFV flag to 0. The TPU has three overflow interrupts,
one for each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The TPU has two underflow interrupts, one each
for channels 1 and 2.
16.5.2 DMAC Activation
The DMAC can be activated by the TGR input capture/compare match interrupt for a channel. For
details, see section 11, Direct Memory Access Controller (DMAC).
A total of four TPU input capture/compare match interrupts can be used as DMAC activation
sources for channel 0.
Rev. 2.00, 03/05, page 712 of 884