SH7615 Datasheet, PDF (835/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

21.3.1 Clock Timing
Table 21.5 Clock Timing
Conditions: V_CC = PLLV_CC = 3.3 V ±0.3 V, PV_CC = 5.0 V ± 0.5 V/3.3 V ±0.3 V, PV_CC ≥ V_CC,
V_SS = PV_SS = PLLV_SS = 0 V, Ta = –20 to +75°C
Item
EXTAL clock input frequency
EXTAL clock input cycle time
EXTAL clock input low-level pulse width
EXTAL clock input high-level pulse width
EXTAL clock input rise time
EXTAL clock input fall time
CKIO clock input frequency
CKIO clock input cycle time
CKIO clock input low-level pulse width
CKIO clock input high-level pulse width
CKIO clock input rise time
CKIO clock input fall time
CKIO clock output frequency
CKIO clock output cycle time
Symbol
f_EX
t_EXcyc
t_EXL
t_EXH
t_EXR
t_EXF
f_CKI
t_CKIcyc
t_CKIL
t_CKIH
t_CKIR
t_CKIF
f_OP
t_cyc
CKIO clock output low-level pulse width
t_CKOL
CKIO clock output high-level pulse width t_CKOH
CKIO clock rise time
t_CKOR
CKIO clock fall time
t_CKOF
CKPO clock output cycle time
t_CKPCYC
CKPO clock output low-level pulse width t_CKPOL
CKPO clock output high-level pulse width t_CKPOH
CKPO clock rise time
CKPO clock fall time
t_CKPOr
t_CKPOf
Power-on oscillation stabilization time
t_OSC1
Standby recovery oscillation stabilization
time 1
t_OSC2
Standby recovery oscillation stabilization
time 2
t_OSC3
PLL synchronization stabilization time
t_PLL
Notes: 1. When PLL circuit 2 is operating
Min
Max
1
31.25
32
8^*1, 12^*2
8^*1, 12^*2
1000
—
—
—
4
—
4
1
31.25
32
8^*3, 12^*4
8^*3, 12^*4
1000
—
—
—
4
—
1^*5, 8^*6
16
4
62.5
1000^*5,
125^*6
3
—
3
—
—
5
—
5
32
1000
11
—
11
—
—
5
—
5
10
—
10
—
10
—
1
—
Unit
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ms
Figure
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
Rev. 2.00, 03/05, page 797 of 884