SH7615 Datasheet, PDF (36/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

16.2.4 Timer Interrupt Enable Register (TIER).............................................................. 678
16.2.5 Timer Status Register (TSR)................................................................................ 680
16.2.6 Timer Counter (TCNT)........................................................................................ 683
16.2.7 Timer General Register (TGR) ............................................................................ 684
16.2.8 Timer Start Register (TSTR) ............................................................................... 684
16.2.9 Timer Synchro Register (TSYR) ......................................................................... 685
16.3 Interface to Bus Master..................................................................................................... 686
16.3.1 16-Bit Registers ................................................................................................... 686
16.3.2 8-Bit Registers ..................................................................................................... 686
16.4 Operation .......................................................................................................................... 688
16.4.1 Overview.............................................................................................................. 688
16.4.2 Basic Functions.................................................................................................... 689
16.4.3 Synchronous Operation ....................................................................................... 695
16.4.4 Buffer Operation.................................................................................................. 697
16.4.5 PWM Modes........................................................................................................ 701
16.4.6 Phase Counting Mode.......................................................................................... 706
16.5 Interrupts........................................................................................................................... 711
16.5.1 Interrupt Sources and Priorities ........................................................................... 711
16.5.2 DMAC Activation ............................................................................................... 712
16.6 Operation Timing.............................................................................................................. 713
16.6.1 Input/Output Timing............................................................................................ 713
16.6.2 Interrupt Signal Timing ....................................................................................... 717
16.7 Usage Notes ...................................................................................................................... 720
16.8 Usage Notes ...................................................................................................................... 730
16.8.1 Clearing Flags in TSR0 to TSR2 ......................................................................... 730
16.8.2 DMA Transfer by TPU0...................................................................................... 730
Section 17 High-Performance User Debugging Interface (H-UDI) ..................... 731
17.1 Overview........................................................................................................................... 731
17.1.1 Features................................................................................................................ 731
17.1.2 H-UDI Block Diagram......................................................................................... 732
17.1.3 Input/Output Pins................................................................................................. 733
17.1.4 Register Configuration......................................................................................... 733
17.2 External Signals ................................................................................................................ 734
17.2.1 Test Clock (TCK) ................................................................................................ 734
17.2.2 Test Mode Select (TMS)...................................................................................... 734
17.2.3 Test Data Input (TDI) .......................................................................................... 734
17.2.4 Test Data Output (TDO)...................................................................................... 734
17.2.5 Test Reset (TRST) ............................................................................................... 735
17.3 Register Descriptions........................................................................................................ 735
17.3.1 Instruction Register (SDIR) ................................................................................. 735
17.3.2 Status Register (SDSR)........................................................................................ 737
17.3.3 Data Register (SDDR) ......................................................................................... 738
Rev. 2.00, 03/05, page xxxvi of xxxviii