SH7615 Datasheet, PDF (513/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Bits 7 to 0—Vector Number Bits 7 to 0 (VC7 to VC0): Set the interrupt vector numbers at the end
of a DMAC transfer. Interrupt vector numbers of 0 to 127 can be set. When a transfer-end
interrupt occurs, the vector number is fetched and control is transferred to the specified interrupt
handling routine. The VC7 to VC0 bits retain their values in a reset and in standby mode. As the
maximum vector number is 127, 0 must always be written to VC7.
11.2.6 DMA Request/Response Selection Control Registers 0 and 1 (DRCR0, DRCR1)
Bit: 7
6
5
4
3
2
1
0
—
—
—
RS4 RS3 RS2 RS1 RS0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W R/W R/W R/W R/W
DMA request/response selection control registers 0 and 1 (DRCR0, DRCR1) are 8-bit read/write
registers that set the DMAC transfer request source. They are written as 8-bit values. They are
initialized to H'00 by a reset, but retain their values in standby mode and a module standby.
Bits 7 to 5—Reserved: These bits are always read as 0. The write value should always be 0.
Bits 4 to 0—Resource Select Bits 4 to 0 (RS4 to RS0): Specify which transfer request to input to
the DMAC. Changing the transfer request source must be done when the DMA enable bit (DE) is
0. See section 11.3.4, DMA Transfer Types, for the possible setting combinations.
Bits RS4 to RS0 are initialized to 001 by a reset.
Bit 4:
RS4
0
Bit 3:
RS3
0
Bit 2:
RS2
0
1
Bit 1:
RS1
0
1
0
1
Bit 0:
RS0
0
1
0
1
0
1
0
1
Description
DREQ (external request)
(Initial value)
Reserved (setting prohibited)
Reserved (setting prohibited)
Reserved (setting prohibited)
Reserved (setting prohibited)
SCIF channel 1 RXI (on-chip SCI with FIFO channel
1 receive-data-full interrupt request)^*1
SCIF channel 1 TXI (on-chip SCI with FIFO channel
1 transmit-data-empty interrupt request)^*1
Reserved (setting prohibited)
Rev. 2.00, 03/05, page 475 of 884