SH7615 Datasheet, PDF (295/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

7.1.5 Address Map
The address map, which has a memory space of 320 Mbytes, is divided into five spaces. The types
and data width of devices that can be connected are specified for each space. The overall space
address map is shown in table 7.3. Since the spaces of the cache area and the cache-through area
are actually the same, and the maximum memory space that can be connected is 160 Mbytes. This
means that when address H'20000000 is accessed in a program, the data accessed is actually in
H'00000000.
The chip has 16-kbyte RAM as on-chip memory. The on-chip RAM is divided into an X area and
a Y area, which can be accessed in parallel with the DSP instruction. See the SH-1/SH-2/SH-DSP
Programming Manual for more information.
There are several spaces for cache control. These include the associative purge space for cache
purges, address array read/write space for reading and writing addresses (address tags), and data
array read/write space for forced reads and writes of data arrays.
Table 7.3 Address Map
Address
Space
H'00000000–H'01FFFFFF CS0 space, cache area
H'02000000–H'03FFFFFF CS1 space, cache area
H'04000000–H'05FFFFFF CS2 space, cache area
H'06000000–H'07FFFFFF CS3 space, cache area
H'08000000–H'09FFFFFF CS4 space, cache area
H'0A000000–H'0FFFFFFF Reserved^*1
H'10000000–H'1000DFFF Reserved^*1
H'1000E000–H'1000EFFF On-chip X RAM area
H'1000F000–H'1001DFFF Reserved^*1
H'1001E000–H'1001EFFF On-chip Y RAM area
H'1001F000–H'1FFFFFFF Reserved^*1
H'20000000–H'21FFFFFF CS0 space, cache-through
area
H'22000000–H'23FFFFFF CS1 space, cache-through
area
Memory
Size
Ordinary space or burst 32 Mbytes
ROM
Ordinary space
32 Mbytes
Ordinary space or
synchronous DRAM^*2
32 Mbytes
Ordinary space,
32 Mbytes
synchronous DRAM^*2, or
DRAM
Ordinary space (I/O
device)
32 Mbytes
8 kbytes
8 kbytes
Ordinary space or burst
ROM
Ordinary space
32 Mbytes
32 Mbytes
Rev. 2.00, 03/05, page 257 of 884