SH7615 Datasheet, PDF (771/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

17.1.3 Input/Output Pins
Table 17.1 shows the H-UDI pin configuration.
Table 17.1 Pin Configuration
Pin Name
Test clock
Test mode select
Test data input
Test data output
Test reset
Abbreviation
TCK
TMS
TDI
TDO
TRST
I/O
Input
Input
Input
Output
Input
Function
Test clock input
Test mode select input signal
Serial data input
Serial data output
Test reset input signal
17.1.4 Register Configuration
Table 17.2 shows the H-UDI registers.
Table 17.2 Register Configuration
Register
Abbreviation R/W^*1 Initial Value^*2 Address
Access Size
(Bits)
Instruction register SDIR
R
H'E000
H'FFFFFCB0 8/16/32
Status register
SDSR
R/W
H'0401
H'FFFFFCB2 8/16
Data register H
SDDRH
R/W
Undefined
H'FFFFFCB4 8/16/32
Data register L
SDDRL
R/W
Undefined
H'FFFFFCB6 8/16
Bypass register
SDBPR
—
—
—
—
Boundary scan
SDBSR
—
—
—
—
register
ID code register
SDIDR
—
H'0101000F —
—
Notes: 1. Indicates whether the register can be read/written to by the CPU.
2. Initial value when the TRST signal is input. Registers are not initialized by a reset
(power-on or manual) or in standby mode.
Instructions and data can be input to the instruction register (SDIR) and data register (SDDR) by
serial transfer from the test data input pin (TDI). Data from SDIR, the status register (SDSR), and
SDDR can be output via the test data output pin (TDO). The bypass register (SDBPR) is a 1-bit
register to which TDI and TDO are connected in bypass mode. The boundary scan register
(SDBSR) is a 330-bit register, and is connected to TDI and TDO in the SAMPLE/PRELOAD or
EXTEST mode. The ID code register (SDIDR) is a 32-bit register; a fixed code can be output via
TDO in the IDCODE mode. All registers, except SDBPR, SDBSR, and SDIDR, can be accessed
from the CPU.
Rev. 2.00, 03/05, page 733 of 884