SH7615 Datasheet, PDF (71/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Section 2 CPU
2.1 Register Descriptions
The register set consists of sixteen 32-bit general registers, six 32-bit control registers, and ten 32-
bit system registers.
This chip is upwardly compatible with the SH-1 and SH-2 on the object code level. For this
reason, several registers have been added to the previous SuperH microcomputer registers. The
added registers are the three control registers: repeat start register (RS), repeat end register (RE),
and modulo register (MOD), and the six system registers: DSP status register (DSR), and A0, A1,
X0, X1, Y0 and Y1 among the DSP data registers.
The general registers are used in the same manner as the SH-1 or SH-2 with regard to SuperH
microcomputer-type instructions. With regard to DSP type instructions, they are used as address
and index registers for accessing memory.
2.1.1 General Registers
There are 16 general registers (Rn) numbered R0 to R15, which are 32 bits in length. General
registers are used for data processing and address calculation.
With SuperH microcomputer type instructions, R0 is also used as an index register. Several
instructions are limited to use of R0 only. R15 is used as the hardware stack pointer (SP). Saving
and recovering the status register (SR) and program counter (PC) in exception processing is
accomplished by referencing the stack using R15.
With DSP type instructions, eight of the 16 general registers are used for the addressing of X and
Y data memory and data memory (single data) using the I bus.
R4 and R5 are used as an X address register (Ax) for X memory accesses, and R8 is used as an X
index register (Ix). R6 and R7 are used as a Y address register (Ay) for Y memory accesses, and
R9 is used as a Y index register (Iy). R2, R3, R4, and R5 are used as a single data address register
(As) for accessing single data using the I bus, and R8 is used as a single data index register (Is).
DSP type instructions can simultaneously access X and Y data memory. There are two groups of
address pointers for designating X and Y data memory addresses.
Figure 2.1 shows the general registers.
Rev. 2.00, 03/05, page 33 of 884