SH7615 Datasheet, PDF (540/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

Clock
DACKn
(Active high)
Address
bus
CPU
Read
command
Row
address
Read
Invalid read
Row Column
address address
DMAC read
(basic timing)
DMAC write
(basic timing)
Figure 11.20 DACKn Output in Synchronous DRAM Single Read
(Auto-Precharge, AM = 0)
Clock
DACKn
(Active high)
Address
bus
Row Column
address address
DMAC write (basic timing)
Figure 11.21 DACKn Output in Synchronous DRAM Write
(Auto-Precharge, AM = 1)
Rev. 2.00, 03/05, page 502 of 884