SH7615 Datasheet, PDF (374/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

The EDO mode bit (EDO) in MCR allows selection of ordinary access/high-speed page mode
burst access or ordinary access/burst access using EDO mode. Since OE control is performed in
EDO mode DRAM access, the CAS and OE pins of the SH7615 must be connected to the OE pin
of the DRAM.
Ordinary access in EDO mode is shown in figure 7.48, and burst access in figure 7.49.
In EDO mode, in order to extend the timing for data output to the data bus in a read cycle until the
next assertion of CASn, the DRAM access time can be increased by delaying the data latch timing
by 1/2 cycle, making it at the rise of the CKIO clock.
This LSI
A1....0 _....
A2
256 k × 16-bit
DRAM
....
A....8
A0
RAS
RD/WR
D31
D16
CAS3
CAS2
D1....5 _....
D0
CAS1
CAS0
CAS/OE
RAS
OE
WE
.... ^I/....O15
I/O0
UCAS
LCAS
....
A....8
A0
RAS
OE
WE
....
I/....O15
I/O0
UCAS
LCAS
Figure 7.46 Example of EDO DRAM Connection (32-Bit Data Width)
Rev. 2.00, 03/05, page 336 of 884