SH7615 Datasheet, PDF (420/925 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperH
RISC engine Family/SH7600 Series

9.2 Register Descriptions
9.2.1 EtherC Mode Register (ECMR)
Bit: 31
30
29
...
19
18
17
16
—
—
—
...
—
—
—
—
Initial value: 0
0
0
...
0
0
0
0
R/W: R
R
R
...
R
R
R
R
Bit: 15
14
13
12
11
10
9
8
—
—
— PRCEF —
— MPDE —
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R/W
R
R
R/W
R
Bit: 7
6
5
4
3
2
1
0
—
RE
TE
—
ILB
ELB
DM PRM
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R/W R/W
R
R/W R/W R/W R/W
The EtherC mode register specifies the operating mode of the Ethernet controller. The settings in
this register are normally made in the initialization process following a reset.
Note:
Operating mode settings must not be changed while the transmitter and receiver are
enabled. To modify the operating mode settings or change the operating mode while the
EtherC is running, first return the EtherC and E-DMAC modules to their initial state by
means of the software reset bit (SWR) in the E-DMAC mode register (EDMR), then make
new settings.
Bits 31 to 13—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 12—Permit Receive CRC Error Frame (PRCEF): Specifies the treatment of a receive frame
containing a CRC error.
Bit 12: PRCEF Description
0
Reception of a frame with a CRC error is treated as an error (Initial value)
1
Reception of a frame with a CRC error is not treated as an error
Note: When this bit is set to 1, the CRC error frame counter register (CEFCR: see section 9.2.14)
is not incremented when a CRC error is detected.
Rev. 2.00, 03/05, page 382 of 884